1. Field of the Invention
The present invention relates to methods and systems for testing Integrated Circuits (ICs).
2. Discussion of the Related Art
ICs are typically manufactured many at a time in the form of dies on a semiconductor material wafer. After manufacturing, the semiconductor wafer is diced, so as to obtain a plurality of IC chips.
Before being shipped to the customers, and installed in various electronic systems, the ICs need to be tested to assess their functionality, and in particular ensuring that they are not defective. In particular, during the test, information regarding global or local physical faults (such as undesired presence of short circuits and break-down events) and more generally the operation of each die, can be detected (for example, by checking the waveform of one or more output signals of each die) so that only the dies that meet predetermined requirements, move to the subsequent manufacturing phases (such as lead bonding, packaging and final testing).
According to a known testing technique, the IC dies are tested before the semiconductor wafer is diced into the individual chips. The test conducted at the wafer level is referred to as “Wafer Sort”.
For example, in case of non-volatile semiconductor memory devices (such as Flash memories) a test known as EWS (Electrical Wafer Sort) is performed on each die wherein the memory device is formed, in order to verify the correct operation thereof.
For performing the test, a tester is used which is coupled to the semiconductor wafer containing the dies to be tested, by means of a probe card which is used for interfacing the semiconductor wafer to the tester.
The tester is adapted to manage signals that are employed for performing the test. Hereinafter, such signals will be referred as test signals and include data signals which are generated by the tester and which are sent to each die to be tested by the probe card, and response signals which are generated by each die in response to the received data signals. The response signals are sent by each die to the tester, which processes them to derive an indication of the proper or improper operation of the die under test.
Often (for example during EWS), probes are employed wherein the electrical coupling of the probe card with the dies to be tested, necessary for achieving the signal exchange, is accomplished through a physical contact. For this purpose, the probe card consists of a PCB (Printed Circuit Board), which is connected to a large number (of the order of some thousands) of mechanical probes, which are adapted to physically contact input/output contact pads of each die to be tested.
However, this type of test system has several limitations; for example, there is the risk of damaging the contact pads of the die under test; also, it has a reduced parallel testing capacity: indeed, when more dies have been tested at the same time, the number of mechanical probes significantly increases, and it may happen that the electrical contacts between the pads and the mechanical probes are not good and electrical discontinuities may take place.
Moreover, when the contact pads are very close to each other, it is very difficult to ensure a good physical contact of the mechanical probes with the pads. Such problem is emphasized when the pads have are small in size and/or a large number thereof is present on each die.
In addition, the mechanical probes are very expensive, and this negatively contributes to the increase of the overall cost of the test system, and eventually of the ICs.
In an alternative, the test signals are, fully or at least in part wirelessly exchanged between the probe card and the dies to be tested, through wireless circuits embedded in the probe card. Typically, each testing site of the wireless probe card comprises at least one transceiver circuit and one or more micro-antennas which are able to communicate with the die through wireless communication, at radio frequency, with corresponding micro-antennas and transceiver circuits integrated on the dies, so as to establish a wireless bi-directional link between the tester and the die under test. In such a way, a wireless test is performed, and the mechanical probes are, fully or in part, eliminated.
A drawback of this solution is that when two or more dies are tested at the same time, there is a cross-talk between the test signals corresponding to different dies. This problem is particularly felt when the dies which have to be tested at the same time are close to each other, possibly adjacent.
In order to avoid cross-talk phenomena, the dies of the semiconductor wafer have to be tested one at a time, but this significantly increases the overall testing time.